The present disclosure relates generally to integrated circuits, such as field programmable gate arrays (FPGAs). More particularly, the present disclosure relates to methods to reconfigure hardened intellectual property (IP) blocks of integrated circuits in an efficient manner.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Integrated circuits (ICs) take a variety of forms. For instance, field programmable gate arrays (FPGAs) are integrated circuits that are intended as relatively general-purpose devices. FPGAs may include logic that may be programmed (e.g., configured) after manufacturing to provide any desired functionality that the FPGA is designed to support. Thus, FPGAs contain programmable logic, or logic blocks, that may be configured to perform a variety of functions on the FPGAs, according to a designer's design. Modern FPGAs also may contain hardened IP blocks. The hardened IP blocks either provide device features that are not implemented in an FPGA core fabric for performance reasons or offer a significant cost or size reduction via feature implementation in the hardened IP blocks. Features that may be implemented on the hardened IP blocks may include hardened memory controllers, digital to analog controllers, analog to digital controllers, phase locked loops, transceivers, High-Speed Serial Interfaces (HSSI), Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA), and the like.
In modern ICs such as FPGAs, there has been limited ability for designers to modify hardened IP blocks at runtime to change behavior or functionality of the hardened IP blocks. The limited modification process for the hardened IP blocks is known as dynamic reconfiguration. Further, modifications derived from dynamic reconfiguration may have involved a great deal of iteration by the designer as well as manual inspection of hardware description language (HDL) code for identifying registers of the hardened IP blocks that are actually modified for a desired function. Accordingly, tool flows that enable the designers to accomplish dynamic reconfiguration may be generally time consuming, error-prone, and complicated to implement and debug.